1. Field of the Invention
The present invention relates to clock recovery systems and methods, and, more particularly, to clock recovery systems and methods for improving jitter tolerance.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional clock recovery system 100. The conventional clock recovery system 100 includes a sampler 110, a phase detector 120, a clock phase modulator 130, and a demultiplexer 140.
The sampler 110 obtains a sample data signal of a serial data input signal. The phase detector 120 detects the phase of the serial data input signal from the sample data signal. The clock phase modulator 130 generates a modulated clock signal by modulating the phase of a reference clock signal REFCLK according to the detected phase. The sampler 110 obtains the sample data signal of the serial data input signal in synchronization with the modulated clock signal. The demultiplexer 140 transforms the sample data signal into a parallel data signal in synchronization with the modulated clock signal.
When applying the conventional clock recovery system 100 to a high-speed data receiving system, phase information regarding the serial data input signal, i.e., transition edge information, is used as a factor in generating a clock signal that helps in receiving the serial data input signal. However, the conventional clock recovery system 100 regards the phase of the serial data input signal detected by the phase detector 120 as an average phase, adjusts an edge of the modulated clock signal to be positioned in the middle of a rising edge and a falling edge of the serial data input signal (the center of the input serial data signal eye), and obtains a sample of the serial data input signal.
However, if a received data signal contains an Inter Symbol Interference (ISI) jitter due to transmission loss characteristics of a transmission line, amplitudes of a high-frequency data signal and a low-frequency data signal are different from each other and, thus, the centers of the transitions are not the same even when transitions in the high-frequency and low-frequency data signals begin at the same position.
FIG. 2 illustrates the positions of edges of a conventional low-frequency data signal and a conventional high-frequency data signal. Referring to FIG. 2, a center 10 of a rising edge of the high-frequency data signal, whose amplitude is less than that of the low-frequency data signal, is positioned to the left of a center 20 of an edge of the low-frequency data signal.
Thus, in the conventional clock recovery system 100 of FIG. 1, when the low-frequency data signal is received after the high-frequency data signal has been continuously received or vice versa, an edge of the clock signal modulated by the clock phase modulator 130 for sampling is positioned at a position corresponding to an edge of the high-frequency data signal or the low-frequency data signal. In this case, because a timing margin of a data signal whose frequency is changed may be insufficient, an error may occur during the receipt of a data signal.